This invention relates generally to semiconductor devices such as RF transistors, and more particularly the invention relates to RF transistors and integrated circuits employing dual metallization (including polysilicon) with a self-aligned first metal layer.
High-power, high-frequency silicon transistors have low pitch or closely-spaced emitter or source sites. As the device pitch or distance between emitter or source sites is reduced, single-layer metallization becomes difficult to employ in device fabrication. Accordingly, a number of dual-metallization schemes has been proposed to relieve the fabrication constraints as well as improve reliability encountered by the single-layer metal system. However, these dual-layer metal systems for high-power, high-frequency devices utilize conventional techniques that require a mask alignment and photoresist patterning of the first and second metal layers with associate problems of image positioning, photoresist development, accuracy of image transfer, and etch. Thus, there exists a need for providing a method of processing dual-layer metal RF power silicon device structures to overcome the problems attendant with prior-art devices and techniques.